Created: Nov 5, 2002
Updated: Nov 22, 2014
SVN Updated: Oct 28, 2012
Other project properties
Development status: Stable
WishBone Compliant: No
Microcontroller core compatible with one used in AT mega 103 and written in VHDL. It has the same instruction timing and the same instruction set (with a few exceptions).
• Core features:
– 32 x 8 general purpose registers
– Twenty three interrupt vectors
– Supports up to 128 Kb of program and up to 64 Kb of data memory
• Peripheral features:
– Programmable UART
– Two 8-bit Timer/Counters with separate prescalers and PWM
– Eight external interrupt sources
– Two parallel ports
The core was tested with several ASM and C programs.
It was implemented in Altera EPF10K50ETC144-3 device and
tested with AVR port of uC/OS-II The Real-Time Kernel, written by Ole Saether.(I used special version of the design with external SRAM for both program and data memories).
Update 22.12.12. Verilog version of the project is uploaded.