Created: Mar 28, 2010
Updated: Oct 23, 2012
SVN Updated: Feb 24, 2011
Other project properties
Development status: Beta
WishBone Compliant: Yes
The OpenCores ao68000 IP Core is a Motorola MC68000 binary compatible processor.
July 2011: Project copied to (https://github.com/alfikpl/ao68000). Further development of ao68000 will continue on github.
- CISC processor with microcode,
- WISHBONE revision B.3 compatible MASTER interface,
- Not cycle exact with the MC68000, some instructions take more cycles to complete, some less,
- Uses about 4750 LE on Altera Cyclone II and about 45600 bits of RAM for microcode,
- Tested against the WinUAE M68000 software emulator. Every 16-bit instruction was tested with random register contents and RAM contents (Processor verification). The result of execution was compared,
- Contains a simple prefetch which is capable of holding up to 5 16-bit instruction words,
- Documentation generated by Doxygen (www.doxygen.org) with doxverilog patch ( http://developer.berlios.de/projects/doxverilog/ ). The specification is automatically extracted from the Doxygen HTML output.
- Version: WISHBONE specification Revision B.3,
- General description: 32-bit WISHBONE Master interface,
- WISHBONE signals described in IO Ports,
- Supported cycles: Master Read/Write, Master Block Read/Write, Master Read-Modify-Write for TAS instruction, Register Feedback Bus Cycles as described in chapter 4 of the WISHBONE specification,
- Use of ERR_I: on memory access – bus error, on interrupt acknowledge: spurious interrupt,
- Use of RTY_I: on memory access – repeat access, on interrupt acknowledge: generate auto-vector,
- WISHBONE data port size: 32-bit,
- Data port granularity: 8-bits,
- Data port maximum operand size: 32-bits,
- Data transfer ordering: BIG ENDIAN,
- Data transfer sequencing: UNDEFINED,
CLK_Isignal: described in Clocks, maximum frequency: about 82 MHz.
- The ao68000 is used as the processor for the OpenCores aoOCS project - Wishbone Amiga OCS SoC ( http://opencores.org/project,aoocs )
It can also be used as a processor in a System-on-Chip booting Linux kernel version 18.104.22.168 up to
initprogram lookup (System-on-Chip example with ao68000 running Linux).
Other free soft-core implementations of M68000 microprocessor include:
- OpenCores TG68 ( http://www.opencores.org/project,tg68 ) - runs Amiga software, used as part of the Minimig Core,
- Suska Atari VHDL WF_68K00_IP Core ( http://www.experiment-s.de/en ) - runs Atari software,
- OpenCores K68 ( http://www.opencores.org/project,k68 ) - no user and supervisor modes distinction, executes most instructions, but not all.
- OpenCores ae68 ( http://www.opencores.org/project,ae68 ) - no files uploaded as of 27.03.2010.
- Microcode not optimized: some instructions take more cycles to execute than the original MC68000,
- TRACE not tested,
- The core is still large compared to other implementations.
- Optimize the desgin and microcode,
- Count the exact cycle count for every instruction,
- Test TRACE,
- Write more documentation.
- April 2010: Tested with WinUAE software MC68000 emulator,
- April 2010: Booted Linux kernel up to init process lookup,
- December 2010: Runs as a processor in OpenCores aoOCS project,
- January 2011: Core area optimization by over 33% (Thanks to Frederic Requin).
- July 2011: Project copied to (https://github.com/alfikpl/ao68000). Further development of ao68000 will continue on github.
Icarus Verilog simulator (
) is required to compile the
Access to Altera Quartus II instalation directory (directory eda/sim_lib/) is required to compile the
- GCC ( http://gcc.gnu.org ) is required to compile the WinUAE MC68000 software emulator,
Java runtime (
) is required to run the
Java SDK (
) is required to compile the
Altera Quartus II synthesis tool (
) is required to synthesise the
soc_for_linuxSystem-on-Chip (System-on-Chip example with ao68000 running Linux).
- ao68000 - the ao68000 IP Core processor,
- MC68000 - the original Motorola MC68000 processor.