Created: Dec 12, 2014
Updated: Dec 24, 2014
SVN Updated: Jan 23, 2015
Other project properties
Development status: Stable
Additional info: Design done , FPGA proven , Specification done
WishBone Compliant: No
is a conceptual implementation of the venerable Zilog Z80 processor targeted to synthesize and run on a modern FPGA device. It differs from the existing (mostly Verilog) Z80 implementations in that it is designed from the ground-up through the schematics and low-level gates. It is a result of a research and tedious reverse-engineering of Z80 at all levels, including micro-photographs of a die.
Project includes a fully working implementation based on this CPU.
It has been described in more details at BaltazarStudios .
- Cycle and bus accurate including the correct behavior of nWAIT and nBUSRQ
- All documented and undocumented opcodes, flags and registers, including R, WZ
- Following the actual arcitectural model down to the individual gates and registers for some modules
- Passes ZEXDOC and ZEXLL (except quirky OTIR/LDIR for IX,IY)
- Correct behavior of BIT n,(HL) to expose WZ
- All interrupts modes (IM0,IM1,IM2)
RTL SimulationDesign is simulated using ModelSim.
- Each module contains a ModelSim project
- Contain individual SystemVerilog test files
- Test wave (*.do) files to quickly set up views
There is a "quick" sanity test as well as a much longer comprehensive test.
Top-level Simulationassember is used to generate Z80 program test snippets which are then run in the simulation and on the actual FPGA hardware. The resulting files should match.
This level of tests adds UART to the ModelSim and FPGA implementation so the tests can be run and outputs compared.
- Tests for various complex instructions like DAA, NEG
- Classic "Hello, World" application
- Tests for interrupt behavior
- ...and more tests embedded in *.asm test files
ImplementationTwo complete and working FPGA designs illustrate implementation and test the A-Z80:
- Basic Computer using keyboard and UART to run Z80 tests
- Complete implementation of a
This design is fully completed, tested and working.
A -based board implementation used about 20% of its LE's.
This implementation is using free Altera tools v13.0.1 Web Edition. It also uses Python 2.7 to build some components and tests.
Although based on Altera devices, this project can be used with other vendors since each (Quartus-specific) schematic file is pre-compiled into a Verilog file.