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Source code


Name: 68hc08
Created: Feb 1, 2007
Updated: Dec 20, 2009
SVN Updated: Jul 16, 2009

Other project properties

Category: Processor
Language: VHDL
Development status: Stable
Additional info: FPGA proven
WishBone Compliant: No

MC68HC08 clone

A MC68HC08 clone in VHDL as single file. Twice performance as the original. Multiplication is done in one clock cycle. Division in two clock cycles.


- feature1
- feature1.1

2007.02.08 first version

tested with C compiler works OK with interrupts
2009.07.16 new version, bugfix at opcode 7E mov ,X+,opr8a X post increment fixed