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Source code

Details

Name: wbicapetwo
Created: May 25, 2015
Updated: May 26, 2015
SVN Updated: Jun 2, 2015

Other project properties

Category: Other
Language: Verilog
Development status: Alpha
Additional info: Design done , FPGA proven , Specification done
WishBone Compliant: Yes
License: GPL

Description

As the title says, this core provides access to the Xilinx Internal Configuration Access Port, Edition 2, via a 32-bit wishbone bus. The ICAPE2 contains address space for 32 registers, and this port provides access to all of them. Specific ports/registers that have been tested and proven include the warm boot start address (WBSTAR) and the command (CMD) register. Using these, together with the Quad SPI Flash core, I can reconfigure my Basys-3 development board from my bedroom nightstand without needing to come into the office and connect a JTAG cable or press the reset button. A very valuable capability therefore.