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Source code


Name: wb_to_amba
Created: Feb 2, 2010
Updated: Aug 30, 2010
SVN Updated: Mar 29, 2011

Other project properties

Category: Other
Language: Verilog
Development status: Stable
Additional info: FPGA proven
WishBone Compliant: Yes
License: LGPL


A AHB master to WishBone slave bridge along with a basic testbench is included. Burst in not yet supported.