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Source code

Details

Name: statled
Created: Sep 8, 2010
Updated: Sep 14, 2010
SVN Updated: Sep 9, 2010

Other project properties

Category: Other
Language: Verilog
Development status: Stable
Additional info: Design done , FPGA proven
WishBone Compliant: No
License: LGPL

Description

A simple module to get the most of your on board heartbeat LED. Change or add more sequences easily in parameters file.