Created: Jun 17, 2008
Updated: Jun 18, 2008
SVN Updated: Mar 10, 2009
Other project properties
Development status: Stable
Additional info: FPGA proven
WishBone Compliant: No
The goal of this project is to provide a simple traffic light controller for different transport modeling purposes like model railways.
I repeat "modeling purposes", don't even think about using it in real-world applications :)
- Very simple, stand-alone Traffic Light Controller
- Through generics parameterizable light timing lengths
- Testbench written in VHDL.
- Makefile for synthesis with XST (Xilinx) and simulation with Modelsim (Mentor Graphics).
The main phase of the project is already finished, but a lot of additional features still need to be added.
- The fixed time control mechanism could be extended with a sensor based dynamic control.
- A parameterizable interface for modeling different kinds of road intersections would be a nice feature.
- Specifications are still needed!