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Source code

Details

Name: simple_pic
Created: Dec 2, 2002
Updated: Mar 4, 2008
SVN Updated: Mar 10, 2009

Other project properties

Category: Other
Language: Verilog
Development status: Stable
Additional info: FPGA proven
WishBone Compliant: Yes
License:

Description

Simple programmable interrupt controller. It supports up to 8 interrupt sources. Polarity and sensitivity (either edge or level) is programmable per interrupt source. The core features an 8bit wishbone interface. Wider wishbone interfaces are easily supported by using multiple instances.
Very simple, very small.

Features

- Up to 8 interrupt sources
- Sensitivity (edge/level) programmable per interrupt source
- Polarity programmable per source
- Static synchronous design
- Fully synthesisable
- 48 LUTs in a Spartan-II, 83 LCELLs in an ACEX

Status

Design is finished and available in Verilog from OpenCores CVS.