Created: Dec 2, 2002
Updated: Sep 7, 2009
SVN Updated: Mar 10, 2009
Other project properties
Development status: Stable
Additional info: Design done , FPGA proven
WishBone Compliant: Yes
Simple General Purpose IO port. It supports up to 8 GPIO pins. Each pin is individually programmable as either input or output. The core features an 8bit wishbone interface. Wider wishbone interfaces are easily supported by using multiple instances (e.g. 4 simple GPIO cores provide a 32bit wishbone interface).
Very simple, very small.
- Up to 8 GPIO pins per core
- Each GPIO pin individually programmable as either input or output
- Static synchronous design
- Fully synthesisable
- 11 LUTs in a Spartan-II, 43 LCELLs in an ACEX
Design is finished and available in Verilog from OpenCores CVS.