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Source code

Details

Name: all_digital_fm_receiver
Created: Mar 14, 2005
Updated: Jan 7, 2012
SVN Updated: Mar 10, 2009

Other project properties

Category: Other
Language: VHDL
Development status: Alpha
Additional info: Design done , FPGA proven
WishBone Compliant: No
License: GPL

Description

The design of the All Digital FM Receiver circuit in this project uses Phase Locked Loop (PLL) as the main core. The task of the PLL is to maintain coherence between the input (modulated) signal frequency, and the respective output frequency, via phase comparison. This self-correcting ability of the system also allows the PLL to track the frequency changes of the input signal once it is locked.
In the new architecture we propose improvement of the new architecture of digital FM demodulator. This work enhances signal quality, system clock frequency, and superior than well known PLL technique today. No more multiplier, no more ROM or table, compact size, and very fast in transient or state response. Real implementation in Altera® APEX20K200 EBC652-1X PLD gives 348 logic elements and run up to 224.42 MHz.

Features

- Frequency modulated input signal is assumed as a series of numerical values (digital signal) via 8-bit of analog to digital conversion (ADC) circuit. The FM Receiver gets the 8 bit signal every clock cycle and outputs the demodulated signal.
- The All Digital FM Receiver circuit is designed using VHDL, then simulated and synthesized using ModelSim SE 6 simulator and Xilinx ISE 6.3i, respectively. FPGA implementation also provided, here we use Virtex2 device. The real measurement is done using ChipScope Pro 6.3i.
- The new architecture is fall into compact size architecture, a new simple demodulation algorithm without multiplier, very fast, running without ROM or look-up table, and takes an absolute stability structure which has no feedback loop for input phase tracking.
- The new architecture enhances signal quality, system clock frequency, and superior than well known PLL technique today. No more multiplier, no more ROM or table, compact size, and very fast in transient or state response. Real implementation in Altera® APEX20K200 EBC652-1X PLD gives 348 logic elements and run up to 224.42 MHz.

Status

- Done in simulation level
- Try to de-modulate real time sound signal