Created: Aug 5, 2008
Updated: Jan 8, 2010
SVN Updated: Nov 16, 2009
Other project properties
Development status: Stable
Additional info: Design done , FPGA proven
WishBone Compliant: No
A scalable synchronous round-robin arbiter. The arbiter is designed to run at reasonable clock speeds with up to hundreds of request lines, and it grants in just a few clock cycles. The arbiter's interface has individual request and grant lines for each requesting device, as well as a binary encoded grant that can be used to control a bus multiplexer.
The basic structure is a tree of small arbiters connected to form a larger arbiter. The tree structure yields linear size scaling and logarithmic delay scaling with respect to the number of request lines. Most of the implementation is in instantiating and interconnecting the arbiter tree. The actual logic boils down to a simple two-input arbiter.
I started this project because I could not find a general purpose arbiter implementation with a configurable number of inputs that scales well. There is not much code for the arbiter implementation. Test benches and a demo instantiation are included. There are also some extras that are not particularly related to the arbiter. I just figured that they would be better off here than anywhere else. It might be better to combine this project with a larger, library type of project, but I did not see such a project in Verilog on OpenCores.
The code is provided under the ISC license, which is a BSD-style license. Everyone is welcome to use and contribute.