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Source code


Name: quad_decoder
Created: Nov 6, 2009
Updated: Jul 12, 2010
SVN Updated: Jul 15, 2010

Other project properties

Category: Other
Language: VHDL
Development status: Beta
Additional info: FPGA proven
WishBone Compliant: Yes
License: LGPL


VHDL Implementation of a quadrature decoder module with a Wishbone bus interface. This module has the following features:
UPDATED per version v1.0.0 Release (July 2010)
-- July, 2010
-- 1)Release version v1.0.0
-- 2)Changes from prior release:
-- a) Bit 3 of the Quadrature Control Register (offset 0x00) is now changed
-- functions, to enable / disable of the Index Zero Count function. When
-- the bit is 0, an index event does not affect the count. When the bit is
-- 1, and index events are permitted, the internal quadrature count is set
-- to 0.
-- b) Added control bit 13, Index Read Count Bit. When set to 0, no count
-- is latched. When set to 1, and index events are permitted, the internal
-- quadrature count is automatically latched to the QRW (offset 0x08)
-- register when an index event is true. This is VERY useful for detection
-- of missed encoder counts, as you can assume that the delta counts in
-- between each index event is fixed, so any deviation from the expected
-- amount indicates that there were missed encoder counts.
-- 3)Tested the FPGA implementation with a real encoder, verified proper
-- operation with count frequencies up to 1.3MHz (50MHz system clock)
-- This test used an instrumented motor driver, with a hardware qudrature
-- decoder in parallel with this encoder module. This module did not miss
-- any counts with a 2048 quad counts / rev encoder running at 40e3 rpm.
-- 4) Fixed a minor bug with the QCR_PLCT bit and the QCR_INZC bit; under
-- a specific condition that both the PLCT bit and the INZC bit were asserted
-- at the same clock cycle, the PLCT would have been executed while the INZC
-- event would have been missed.
-- 5) Added an additional feature: Quadrature Count Compare Match Event;
-- when the CCME bit is set in the QCR register, and the quadrature count
-- matches the QRW register, a signal is asserted and the status bit of the
-- QSR register is set. This event can also generate an interrupt.
PREVIOUS UPDATES------------------------------------------------------------
--Wishbone module for interfacing to optical encoders
--4X Quadrature decoding of encoder signals
--Programmable external interrupt request output
--Dedicated 'latch quadrature count' input for multi-axis syncronization
--Memory mapped control, status, and count registers
--Verified on a Xilinx FPGA with a soft core processor (Altium TSK3000)