Created: Sep 25, 2001
Updated: Mar 10, 2013
SVN Updated: Mar 10, 2009
Other project properties
Development status: Stable
WishBone Compliant: No
The PS/2 interface project (ps2_interface) is interface hardware to allow using a ps2 mouse or keyboard in your project. The code is written in Verilog, and was sythesized into a Xilinx SpartanII XC2S200 chip. Debugging was done with an HP16500 series logic analyzer, and there is no testbench for these interfaces.
For the keyboard interface, there is translation from scan codes into ASCII characters, for those scan codes that have ASCII equivalents. Also, the keyboard interface traps the left/right shift scan codes, and produces uppercase ascii when appropriate. This means that the keyboard interface can be used with a serial port core to create an ASCII terminal type of interface on chip. The keyboard interface is bi-directional, so the user can send commands to change the operation of the keyboard, or light up the "Num Lock", "Caps Lock" and "Scroll Lock" LEDs as desired.
The mouse interface implements "hot plugging" of the mouse. This means that the mouse may be unplugged and then re-connected, and the interface hardware will recognize this, and issue the command to put the mouse into "streaming mode" so that it starts sending out data packets. The position updates from the mouse are provided in terms of two 10-bit signed quantities: an X-increment and a Y-increment. In actual use, the Y-increment appears to be negative of the sense you would expect (i.e. moving the mouse up produces a negative increment...) For simplicity, this interface only sends one command to the mouse, which is the command to put it into streaming mode.
The design team of ps2_interface welcomes any kind of help and feedback on these cores. If you are interested in further development of this project, please contact us.
- These cores have been coded completely, synthesized and tested for correct operation (and debugged!) inside a Xilinx XC2S200 chip. The tools used for development were the Xilinx Foundation 3.1i (non-ISE) tools.
- These cores were also tested using the free Xilinx Webpack ISE (9/10/01) tools. However, the "rs232_syscon.v" module has to be modified to work with ISE (only important for the "soc" type downloads). The ASCII characters must be coded as numbers in ISE...
- There are no technology-dependent elements used in these cores.
- The cores consume about 100 Xilinx Virtex slices each (depending on parameters)
- The cores are parameterized to allow changing timer values to accomodate different clock speeds.
- The code has comments. The interface to the mouse and keyboard use tri-state I/O for the bi-directional clk and data lines. These lines must have pullup resistors! (the value is not very critical.)
- The interface is currently implemented using state-machines (no processor is involved.)
- "Debounce" states are provided in the state machines, to make the interfaces more tolerant of different types of mice and keyboards.
In the future, a bare bones version of the keyboard interface could be implemented which implements only receive, to save on resource utilization and eliminate the bi-directional interface. For the mouse interface, this is impossible, since the mouse requires a "streaming mode" command in order to begin sending its data packets.