Created: Jun 22, 2009
Updated: Dec 20, 2009
SVN Updated: Jul 9, 2009
Other project properties
Development status: Stable
Additional info: Design done , FPGA proven
WishBone Compliant: No
LFSR Counter Generator is a command-line application that generates Verilog or VHDL code for an LFSR counter of any value up to 63 bit wide. The code is written in C and is cross-platform compatible.
There is an online version of the tool at OutputLogic.com
It's more convenient to access, but the online tool is slower to generate the code for large counter values.