Created: Aug 5, 2003
Updated: Dec 20, 2009
SVN Updated: Mar 10, 2009
Other project properties
Development status: Stable
Additional info: FPGA proven
WishBone Compliant: No
The aim of this Core is to track the first file saved
into a FAT16 volume and to read the information from it offering those data to a Wishbone bus trough a Wishbone slave interface. The Core has an IDE interface that permits the attachment of devices as Compact Flash (no DMA support). It uses about 300 Xilinx Spartan II slices (if Area optimization is chossen about 285).
Internally it has two Modules that can be used indepently. Both of them are implemented using a Picoblaze Programmable State Machine, using Xilinx BlockRams for instructions. Those modules are:
1 - HOST ATAPI UNIT (HAU): Controls IDE signals and manages the ATAPI protocol for sector reading. For a sector read, it only needs the LBA (Logic Block Address) as input, answering with the words of that sector. This module can be used in embedded systems that do not require any specific FAT format. As the control state machine is implented in "software", modifications (write support, for example) are easy to implement.
2 - FAT PROCESSOR UNIT (FAU): It requests to HAU the necessary sectors to track and read the first valid file which has been stored into the IDE device that uses a FAT16 volume.
DESCRIPTION: FFR16 internal module division and interfaces
- Small area requeriments.
- Written in VHDL and in KCPSM assembler.
- Co-simulation facilities (KCPSM assembler generates VHDL simulable file).
- Mix & Run in SoPC due to the use of a Wishbone interface is used. Spartan II and 50 Mhz clock
- Design is finished and available in VHDL from OpenCores CVS.
- Documentation is no still available.