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Source code


Name: sigma_delta_dac_dual_loop
Created: Oct 16, 2012
Updated: May 1, 2014
SVN Updated: Oct 16, 2012

Other project properties

Category: Other
Language: VHDL
Development status: Mature
Additional info:
WishBone Compliant: No
License: Others


Public domain code of the 2nd order Sigma-Delta DAC. Allows to produce reasonable quality audio signal from single digital ouput pin in the FPGA.
The resource consumption is very low (24-bit version of the DAC consumed 5% of slices in xc3s200).

Detailed description

This project implements 2nd order DAC, which I have created when I needed to add the voice output to one of my FPGA based systems.
The converter generates 1-bit digital signal on the dout output. You need to connect a simple RC lowpass filter to convert it into the analog signal.
There are directories containing two different implementations:

allows to obtain higher clock frequency, and therefore higher oversampling ratio, but number of rising and falling slopes in time unit depends on signal value. Therefore you may experience nonlinear distortions if those two slopes are not symmetrical.
The output of the DAC is updated once every three clock pulses. If there is a '1' on the DAC output, the sequence '110' is generated on the dout output. If there is a '0' on the DAC output, the sequence '100' is generated. Therefore we always have one rising slope and one falling slope generated in each DAC cycle. Unfortunately this implementation accepts lower clock frequencies, so the oversampling ratio is lower
Additionally in each directory there are two equivalent implementations.
The first one (dac_dsm2v.vhd, dac_dsm3v.vhd) uses the variables in the process (which maybe not acceptable for some synthesis tools).
The second one (dac_dsm2.vhd, dac_dsm3.vhd) is slightly less readable, but should be easier to synthesize.
The top entity (dac_dsm2_top.vhd, dac_dsm3_top.vhd) instantiates the DAC for synthesis (however before synthesis you should set the number of bits, setting the default value of the "nbits" generic).
For the dac_dsm2_top.vhd with Xilinx ISE 9.2 i've got the following results: Speed oriented synthesis for device xc3s200, package ft256, speed -5 resulted with 100MHz clock at 4% slice utilization (so you can get even 1000 oversampling ratio for 100kHz sampling frequency).
Synthesis of 24-bit version of the DAC resulted for the same chip in 5% slice utilization and also 100MHz fclk max.
To check DAC performance without putting it into real hardware, you can run "make" command in the appropriate directory (it requires free tools: ghdl, python and pylab). You'll see the spectra of the output signal (before low pass filtering) consisting of three sinusoids.
The first version of this DAC was published in the alt.sources group as "VHDL source for Sigma-Delta DAC converter with dual loop". This post is archived in the Google groups and in the funet archive .
All sources are published as PUBLIC DOMAIN.