Created: Oct 17, 2008
Updated: Sep 4, 2009
SVN Updated: Mar 10, 2009
Other project properties
Development status: Stable
Additional info: FPGA proven
WishBone Compliant: Yes
This is a ZBT SRAM controller which is Wishbone rev B.3 compatible (classic + burst r/w operations).
PLEASE NOTICE THAT THIS CORE IS LICENSED UNDER http://creativecommons.org/licenses/by-nc-sa/3.0/ (Creative Commons Attribution-Noncommercial-Share Alike 3.0 Unported). That means you may use it only for NON-COMMERCIAL purposes.
It has been simulated and verified on a Xilinx Virtex-5 FPGA board of type ML-506.
This core is Wishbone compliant, using registered feedback cycles.
The only quirk is that, in burst operations, the "wb_tga_i" input must be '0' during the last (or single) 4 words burst (the last four clock cycles, being the fourth the one in which wb_cti = "111" indicates the WB end of burst).
In short: keep "wb_tga_i" low unless you want to read 4 more words in another burst immediately following the current one.
This is necessary in order to make the perfect overlap between ZBT read/write burst cycles and Wishbone's registered feedback cycles.
It is fully functional, but any bug reports are very welcome.
In the next image a typical multiple burst operation is shown (it's the same for read/write, so wb_we_i, wb_dat_i, wb_dat_o are omitted for clarity), where 12 words are read from memory, which means 3 bursts of 4 words each.
1.- In the first cycle (the first one where wb_cti_i="010") signals wb_cyc_i, wb_stb_i, wb_adr_i, wb_we_i and wb_dat_i (for writes) are set.
2.- As we are going to read/write 3 bursts (of 4 words each), the wb_tga_i signal must be at '1' during the first two bursts.
3.- Don't change any signals until wb_ack_o rises.
4.- When wb_ack_o = '1' then increment wb_adr_i every cycle.
5.- (This is the only step not in the WISHBONE specs.) After the first two bursts are done, lower the wb_tga_i signal in order to signal the ZBT SRAM Controller that the last burst starts now.
6.- In the last cycle wb_cti_i must be "111" to signal a Wishbone end of burst and, after that, wb_cyc_i and wb_stb_i must be lowered (or stay risen in order to initiate a new transaction).
The fifth step is the only one not in the WB specs. for registered feedback cycles. The rest are normal operation as defined in the specifications.
- This core differs from others at OpenCores in that it makes the best overlap between Wishbone registered feedback burst cycles and the ZBT SRAM burst R/W cycles, so that the fastest access (a continuous burst) can be achieved.
- Also Wishbone classic cycles can be used (for single word R/W) although the core wasn't optimized for them (i.e.: for a read, it takes three wait cycles to output a single word).
- 17/10/2008: I'll upload the source and testbench in a few days (after cleaning it up a bit ;)
- 30/10/2008: Source code uploaded (pending to do a nice Wishbone documentation)
This core has been developed under a project of the Spanish Ministry of Science.
DESCRIPTION: Datasheet for ISSI IS61NLP ZBT SRAM (used in Xilinx ML506 board)