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Source code

Details

Name: dram
Created: Sep 25, 2001
Updated: Dec 20, 2009
SVN Updated: Mar 10, 2009

Other project properties

Category: Memory core
Language:
Development status: Stable
Additional info:
WishBone Compliant: No
License:

Description

Parameterisable DRAM model, i.e. scalable data and address widths. Simulation assertions can be toggled on/off. Uses !RAS/!CAS control sequence for modelling DRAM activity. Refresh is monitored with data corrupted to "UU ... "

Status

- VHDL code is available (see Downloads)

Author

- Damon P Thompson