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Name: open_free_list
Created: Jan 31, 2010
Updated: Feb 16, 2010
SVN Updated: Feb 16, 2010

Other project properties

Category: Memory core
Language: Verilog
Development status: Beta
Additional info:
WishBone Compliant: No
License: LGPL

Description

Open FreeList Readme

The Open FreeList module is used to manage a set of variable sized packets inside a fixed memory block. The memory block is partitioned into fixed sized chunks and each packet uses one or more chunks. The module offers three possible actions:

  1. Write a packet into memory
  2. Read a packet from memory
  3. Release a packet

Parameters

Name Description Unit Default Value
RAM_W Memory block width bits 128
RAM_E Memory block extra data bits 0
RAM_S Memory block size KBytes 64
CHK_S Chunk size Bytes 128
RAM_TYPE Memory block type string "MRAM"
FL_AEMPTY_LVL FreeList almost empty level # 2

Interface

Name Direction Width Description
global signals
reset_n input 1 async reset (active low)
clk input 1 clock
write interface
fl_q output clog(#_of_chunks) first chunk number for a new packet.
capture this value and use it to read/release the packet
fl_aempty output 1 indicates that the number of chunks reached the almost empty level
fl_empty output 1 no more chunks available. do not write any more
wren input 1 write pulse. writes the data on din into the memory block
din input RAM_W+RAM_E data to write into memory block
eop input 1 end-of-packet indication. assert on last write of packet
read interface
chunk_num input clog(#_of_chunks) first chunk in a packet to be read or released
load_req input 1 request to read a packet starting at chunk number 'chunk_num'
rel_req input 1 request to release a packet starting at chunk number 'chunk_num'.
also required after a packet is read
load_rel_ack output 1 acknowledge a read or release request
rden input 1 read request. data on 'dout' is valid one clock later
dout output RAM_W+RAM_E data read from memory block

Operations

Write

To write a packet, do the following:

  • make sure 'fl_empty' is de-asserted
  • capture the value on 'fl_q'. it will be used later to reference this packet
  • while 'fl_empty' is not asserted do:
    • write the next data line in 'din'
    • assert 'wren'
    • on the last line of the packet, assert 'eop' as well

Read

To read a packet that was previously written, do the following:

  • set 'chunk_num' to the value of the first chunk in the packet.
    this value was obtained from 'fl_q' when the packet was written
  • assert 'load_req'
  • when 'load_rel_ack' is asserted, for each line of data do:
    • assert 'rden'
    • capture 'dout' one cycle later
To determine the last line of data, you could:
  • store the packet length in an external structure
  • use the extra bits in the memory block to hold an indication such as end-of-packet

Note that the 'eop' indication that is written in the write operation is not available on a read operation.

after a read is complete, a release operation must be explicitly performed. There is no need to set the 'chunk_num' value after a read operation. The chunks are released when the packet is read, but the last chunk requires an explicit release operation.

Release

A packet can be released under two circumstances:

  1. when a read is complete, a release must be issued
  2. if a packet is not needed, it can be released without reading it
To release a packet, do the following:
  • set 'chunk_num' to the first chunk of the packet (not required after a read)
  • assert 'rel_req'
  • when 'load_rel_ack' is asserted, you are done

Memories

Three memories are used in this module:

  1. ram - dual port memory. two cycles to read
  2. free_list - single clock lookahead FIFO
  3. link_list - dual port memory. two cycles to read
The target architecture is Altera Sratix. There should be matching memory blocks in other architectures.


Code: Alex Manash - Crescendo Networks
Docs: Amit Fridman - Crescendo Networks