Created: Oct 26, 2008
Updated: Aug 26, 2010
SVN Updated: Aug 26, 2010
Other project properties
Development status: Stable
Additional info: Design done , FPGA proven , Specification done
WishBone Compliant: No
HPDMC is part of the
, the most advanced open source SoC for interactive multimedia applications.
Fast DDR SDRAM controller with features targeted at high-bandwidth burst-oriented applications such as live video processing. The core has been re-used by several projects and institutions, such as the NASA as part of a software-defined radio system for the ISS (CoNNeCT experiment).
- Current design is targeted at 32-bit wide DDR SDRAM.
- Dedicated non-standard high-speed bus for efficient memory access (FML).
- Pipelined accesses to hide DRAM latencies.
- WISHBONE to FML bridge available with cache support.
- FML arbiter with pipelining support available for high-speed DMA.
- Fully synchronous controller (memory clock = controller clock) to avoid clock domain crossing latencies.
- CSR bus interface for configuration.
- Low level interface to the SDRAM chip is possible ("bypass" mode).
- SDRAM initialization sequence performed by the system CPU to save hardware resources and maximize flexibility.
- Timing parameters configured at runtime.
- Page hit detection supports multiple open banks.
- Automatic refresh with programmable refresh interval.
- CSR bus specifications
- FML bus specifications