Created: Sep 24, 2002
Updated: Jul 29, 2011
SVN Updated: Mar 10, 2009
Other project properties
Development status: Stable
Additional info: FPGA proven
WishBone Compliant: No
Generic, multi-purpose FIFOs. Available as single clock and dual clock version, binary, lfsr, and gray encoded (dual clock only). All are parameterizable and use generic_memories for memory. These FIFOs are fully portable from FPGAs to ASICS.
- Written in Verilog
- Fully Synthesizable (FPGA & ASIC libraries)
- Single and Dual Clock
- All FIFOs that are release are done. They have been simulated and most of them have been used in one way or another in one of my projects. Some have been verified in real hardware.
- October 2003, Added a dual clock FIFO that is gray code encoded (fully parameterizable)
To use this IP core, you must also download the generic_memories models. Download here
This IP Core is provided by:
www.ASICS.ws - Solutions for your ASIC/FPGA needs -