Created: Oct 22, 2011
Updated: Oct 23, 2011
SVN Updated: Oct 23, 2011
Other project properties
Development status: Alpha
WishBone Compliant: No
CFI flash controller IP.
Provides two modes of operation - simple (Wishbone bus straight through to flash bus, essentially, but with 32-bit word read capability, allowing XIP - execute in place - for 32-bit processors) and a "CFI engine" mode, which aims to simplify interfacing with a CFI flash.
Only implements asynchronous flash bus interface.
System bus interface is Wishbone, or CFI engine module can be used stand-alone and provides a generic bus interface.
Both modes tested with Intel P30 Strataflash part on Xilinx ML501 board.
Is implemented in the ORPSoC ml501 board port. A software driver for, and programming utility using this core can also be found in ORPSoC. XIP has been tested and works for OR1200 processor in ORPSoC.
Simple mode has been found to work fine with Strataflash drivers found in u-boot and Linux.
See the README under the doc/ path for further information.