Created: May 25, 2015
Updated: May 26, 2015
SVN Updated: Jun 2, 2015
Other project properties
Development status: Alpha
Additional info: Design done , FPGA proven , Specification done
WishBone Compliant: Yes
This core offers a real-time clock capability to a device. Specific capabilities include 24-hour BCD time, a count down timer, a stop watch, an alarm, and an ability to precisely capture the time of an externally generated event.
Other outputs include drivers for 16 LED's that will count up to each minute, 32 bits to control four digits of a seven segment display, and an interrupt strobe line which can be used to set off and edge triggered interrupt whenever the countdown timer gets to zero or the alarm goes off.
The core is very versatile, depending internally on incrementing a 48-bit counter with a user controlled increment. This allows the clock to keep track of time no matter what fundamental speed your underlying clock is run at, from 66kHz all the way up to 250 THz.
The entire clock is controlled via 8 registers on a 32-bit wishbone bus. Please see the spec.pdf sheet within the docs/ directory for more information.