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Source code

Details

Name: rs_5_3_gf256
Created: Oct 19, 2004
Updated: Jun 20, 2005
SVN Updated: Mar 10, 2009

Other project properties

Category: ECC core
Language: Verilog
Development status:
Additional info: Design done
WishBone Compliant: No
License:

Reed Solomon (5, 3) Encoder-Decoder in GF(256)

- Symbol width : 8-bits.
- Encodes every 3-byte message into 5-byte codewords.
- Capable of correcting any single symbol error (even if all the 8-bits are erronous) in a codeword.
- This core has two operation modes: Encoding and Decoding.
- In both operation modes, the inputs are taken in byte-by-byte at each clock cyle.
- While encoding, message is input at three clock cycles and the next two clock cyles are reserved for the two parity symbols of the codeword.
- While decoding, received vector is taken in at five clock cycles. But the output is first seen at the sixth clock cyle. However, at the sixth clock cycle another received vector can be fed to the decoder.

Features

- 24 bits of information is encoded at every 5 clocks:
- example: Clock Frequency : 50 MHz --> Baud: 240Mbps
- 32 bits of received vector is decoded every 5 clocks:
- example: Clock Frequency : 50 MHz --> Baud: 320Mbps
- Please go to the "downloads" link and have look at the ppt file.

Status

- status1
- status2