Created: Dec 8, 2007
Updated: Dec 17, 2007
SVN Updated: Mar 10, 2009
Other project properties
Development status: Stable
WishBone Compliant: No
PCI express CRC verilog code 16 bit data 32 bit CRC
Designers commonly use Cyclic Redundacy Codes (CRC) as an alternative to parity and checksum calcutions for checking and correcting errors in data transmissions.
The CRC method for error detection and correction treats the data frame as a huge binary number. The binary number is divided (at the CRC generation end) by a fixed binary number (the CRC generator polynomial) and the resulting remainder of this division (CRC value) is appended to the end of the data frame. The receiver upon reception of the data frame repeats the calculation and compares its calculated CRC value the CRC value attached to the data frame. The traditional method for implementing a CRC generator uses a shift register with XOR gates and feedback taps.
The classic serial implementation is widely used, but it is too slow for PCI Express LCRC and Gigabit Ethernet where bit rates can top 100 Mb/sec. The alternative method is parallel CRC calculations. This parallel conversion effectively divides the input clock frequency by 8, 16, or 32.
-feature1 Verilog LCRC code for PCI Express TLP packets
-reature1.1 16 bit data in 32 bit LCRC out