Go Back

Source code

Details

Name: hamming_gen
Created: Oct 27, 2006
Updated: Mar 21, 2013
SVN Updated: Mar 10, 2009

Other project properties

Category: ECC core
Language: VHDL
Development status: Stable
Additional info:
WishBone Compliant: No
License: GPL

Description

This C++ program generates VHDL package with hamming encoder and decoder. It also generates a simple testbench that can be used to evaluate the generated Hamming code.
my email is ale_amory@opencores.org

Features

- It is a easy to use command-line program - HammingGen \ \ \ - It generates two types of Hamming code - SEC - Single Error Correction - SEC-DED - Single Error Correction and Dual Error Detection - It is easy to modify the original design

Examples

Generated Code for a Hamming SEC with 32 bits - FUNCTION hamming_encoder_32bit(data_in:data_ham_32bit) RETURN parity_ham_32bit; - FUNCTION hamming_decoder_32bit(data_parity_in:coded_ham_32bit) RETURN data_ham_32bit; Consider the folowing resgister description library ieee; use ieee.std_logic_1164.all; entity test is port ( datain : in std_logic_vector(15 downto 0); clock : in std_logic; dataout : out std_logic_vector(15 downto 0); error : out std_logic_vector(1 downto 0) ); end entity ; architecture test of test is signal temp : std_logic_vector(15 downto 0); begin process (clock) begin if (clock'event and clock='1') then temp end if ; end process ; dataout end architecture ; The fault-tolerant version of this code is: library ieee; use ieee.std_logic_1164.all; use WORK. .all; entity test is port ( datain : in std_logic_vector(15 downto 0); clock : in std_logic; dataout : out std_logic_vector(15 downto 0); error : out std_logic_vector(1 downto 0) ); end entity ; architecture test of test is signal temp : ; begin process (clock) begin if (clock'event and clock='1') then temp ; end if ; end process ; dataout ; end architecture ;

Future Features

- Support correction of more than one faults