Details
Name: fir_wishbone
Created: Sep 10, 2013
Updated: Mar 4, 2014
SVN Updated: Mar 30, 2015
Other project properties
Category:
DSP core
Language:
VHDL
Development status:
Beta
Additional info:
FPGA proven
WishBone Compliant: Yes
License: LGPL
Description
This FIR filter is very generic and flexible. It has been tested working on an FPGA, though the existing version does not yet have a Wishbone control interface. I will be adding one to it soon. Stay tuned!