Created: Apr 12, 2012
Updated: Apr 13, 2012
SVN Updated: Apr 13, 2012
Other project properties
Development status: Stable
WishBone Compliant: No
This is an elementary generic structural VHDL code for FIR digital filters in transposed-form and direct-form implementations.
This project covers a wide spectrum of design aspects, in particular design and both functional and formal verification.
The project is developed in VHDL and modeled in SystemC. The SystemC model is used for functional and formal verification.
TCL scripts for GHDL and SystemC is included within the project files.
This code could be considered for VHDL classes or DSP classes for amateurs or beginners.
The developed code was synthesized for FPGA and ASIC (0.13um CMOS) using:
Synopsys Design Compiler
Cadende RTL Encounter
Further, it was implemented using Xilinx Spartan-3E FPGA utilizing the Spartan-3E Starter Kit. It was tested using Xilinx ChipScope and a complete lab setup, as well. The filter output was converted to analog output using the on-board DAC to trace it on a Spectrum analyser.