Details
Name: fht
Created: Apr 11, 2007
Updated: Dec 18, 2010
SVN Updated: Mar 10, 2009
Other project properties
Category:
DSP core
Language:
Verilog
Development status:
Beta
Additional info:
Design done
WishBone Compliant: No
License:
Description
The RTL computes Fast Hadamhard Transform of 8-bit input data. The code has been developed using standard FHT algorithm using matrix addition. The code has been functionally verified and also synthesized for Xilinx FPGA.
Features
- feature1
- feature1.1
-feature1.2
-feature2
Status
- status1
- status2