Created: May 20, 2004
Updated: Dec 17, 2012
SVN Updated: Mar 10, 2009
Other project properties
Development status: Beta
Additional info: Design done
WishBone Compliant: No
This is a collection of SHA(Secure Hash Algorithm) cores. These include SHA-1, SHA-2 algorithms.
These cores are non-pipelined version of SHA, and have simple interfaces with the host side.
- Support SHA-1(160), SHA-2(256/384/512)
- Use a simple 32-bit I/O bus interface
- High performance
- Share hardware between different SHA processing
- Can operate up to 200MHz at 0.18um Standard cell design
- Written in VerilogHDL
- Initial release
- Combine SHA1/SHA2 in a single core
- Make it smaller and faster!