Created: Jun 28, 2008
Updated: Dec 20, 2009
SVN Updated: Mar 10, 2009
Other project properties
Development status: Beta
Additional info: FPGA proven
WishBone Compliant: No
This IP core loads an unsorted, encrypted list of numbers from memory. It then decrypts and sorts the list.
Sorting is acheived using a high-throughput, heavily parametric mergesort core.
- Highly parametric mergsort core
- folds a single comparator across multiple fifos mapped onto SRAMs
- compartor scheduler as a parameter
- High speed PLB master core
- achieves effective memory throughput of more than 400MB/s
- uses configurable burst transfers to obtain high throughput
- Pipelined AES core
This project is completed and development is closed. It has been successfully implemented on FPGA.