Created: May 17, 2009
Updated: Apr 20, 2013
SVN Updated: Apr 19, 2014
Other project properties
Development status: Stable
Additional info: Design done , FPGA proven , Specification done
WishBone Compliant: No
I know there are plenty of AES (Rijndael) implementations around. I created my own anyway because I was unhappy with either the implementation language (I don't know Verilog and I think its an ugly language), the documentation or the performance/resource usage of the ones I found on the net.Here are the key parameters for this core:
- strictly modular design
- generics for the keylength (128,192,256 Bit) and enabling and disabling of decrypt datapath.
- Avalon Interface tested with niosII (can be adapted to match wishbone (I have no whishbone CPU so I didn't test)) - Interrupt or polling behaviour
- The ressource usage is IMHO ok for 128 Bit encrypt only version (797 LE on a CylconeII). (There is work to do to achieve better f_max and ressource usage for the cores with both encrypt and decrypt datapath)
- documentation available : Datasheet
1.) @anybody with Wishbone experience: can you write an interface or adapt it to whishbone? It should be no problem for the standard signals, however I found no clue how to handle IRQ for wishbone.
Possibly check it with openrisc?
2.) Write a VHDL configuration for choosing the architectures used in the generate statements. especially to switch between Altera M4K-Block bases sbox-ROMs and generic ones.
3.) Increase performance for configurations with both encrypt and decrypt datapath. currently keyexpansion is shared and result signals are multiplexed which leads to drastic decline of f_max. (95MHz for encrypt vs. 65MHz for encrpyt+decrypt).