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Source code

Details

Name: aes_all_keylength
Created: Jun 24, 2013
Updated: Aug 10, 2014
SVN Updated: Sep 15, 2014

Other project properties

Category: Crypto core
Language: VHDL
Development status: Alpha
Additional info:
WishBone Compliant: No
License: LGPL

Description

Four stage pipeline design working at 361.890MHz on Xilinx's 28nm Kintex 7 speed grade 3 FPGA device. Calculating 4 blocks parallely, encrypting up to 4.25 Gbits data per second (0.361Ghz* 4 stage pipe * 128 bits parallel / 44 cycles a block).