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Source code

Details

Name: systemcaes
Created: Jul 2, 2004
Updated: Apr 9, 2010
SVN Updated: Mar 10, 2009

Other project properties

Category: Crypto core
Language: Verilog
Development status: Stable
Additional info: FPGA proven
WishBone Compliant: Yes
License:

Features

- SystemC and Verilog code is provided
- Verified using TLM(Transaction Level Modelling Style)
- Encoder and decoder in the same block
This work is given by Universidad Rey Juan Carlos (Spain)
www.gdhwsw.urjc.es

Status

- 128 bits low area implementation uploaded
- 192 bits low area implementation uploaded

Description

Here you can find two different implementations of AES encryption algorithm:
- A 128 bits AES algorithm focusing on very low area applications.
- A 192 bits AES algorithm focusing on very low area applications.
The 128 bits low area implementation takes about 500 cycles to encrypt/decrypt a block.
The 192 bits low area implementation takes about 280 cycles to encrypt/decrypt a block.
They don't use memories to store the S-box and have many other architectural improvements to reduce the area comsumption.
Implements the encoder and decoder in the same block.
The cores were written in SystemC RTL, and verified using TLM(Transaction Level Modelling Style).
Verilog synthesizable code is also provided
All implementations have been tested on a Xilinx Virtex2 FPGA succesfully.