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Source code

Details

Name: a_vhdl_can_controller
Created: Aug 23, 2007
Updated: Oct 31, 2014
SVN Updated: Mar 10, 2009

Other project properties

Category: Communication controller
Language: VHDL
Development status: Stable
Additional info: Design done
WishBone Compliant: No
License:

Description

A (as far as I know) untested VHDL translation of the Verilog Can protocol Controller
To Download, click at the "Downloads" button upper right part of this page
This project is a translation Igor Mohor's Verilog http://opencores.org/project,can,overview (CAN Protocol Controller)

Features

The modules have "_vhdl_" added to their names, to ease compare simulation with Verilog version (for those with mixed a language simulator)

Status

use at own risk - have no had time to test/simulate
check the Philips SJA1000 data sheet and the http://opencores.org/project,can,overview (Verilog project page) for more information