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Source code

Details

Name: uart_block
Created: Apr 20, 2012
Updated: May 5, 2012
SVN Updated: May 12, 2012

Other project properties

Category: Communication controller
Language: VHDL
Development status: Mature
Additional info: FPGA proven , Specification done
WishBone Compliant: Yes
License: LGPL

Description

Simple uart core with wishbone slave interface and programmable baud rate generator, based on clock speed and desired baud rate