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Source code

Details

Name: systemverilog-uart16550
Created: Mar 30, 2010
Updated: May 5, 2010
SVN Updated: May 1, 2010

Other project properties

Category: Communication controller
Language: Verilog
Development status: Alpha
Additional info:
WishBone Compliant: Yes
License: LGPL

Description

RS232 Protocol 16550D uart (mostly supported)
- language : systemVerilog IEEE 1800-2005 (Quaruts2-9.1sp1 Support)
- scale : fpga cyclone3 800cell, >50Mhz
- bus : wishbone
-

TODO:

Lin's automotive standards
-> subset of transport layer circuit