Created: Jan 20, 2002
Updated: Aug 26, 2010
SVN Updated: May 6, 2009
Other project properties
Development status: Mature
WishBone Compliant: Yes
Design in VHDL:
This UART is able to Transmit/Receive bytes in the configuration:
1 start bit - no parity - 1 stop bit.
It can be commanded by a microcontroller, or by other IP core.
It is not suited to interface a modem as there is no control handshaking (CTS/RTS).
It does'nt contain FIFO for emit/receive.
• WISHBONE interface in 8-bit data bus
• Two clock: one for wishbone interface, one for RS232 bitstream generation
• Baudrate divisor from 1 to 65536 (generic parameter set at integration time)
• Spartan: XCS10-TQ144-4: 71 flip-flop
• Spartan-II: XC2S15-CS144-6: 153BELs@107MHz