Created: Mar 6, 2012
Updated: Nov 12, 2014
SVN Updated: May 7, 2013
Other project properties
Language: Verilog & VHDL
Development status: Beta
Additional info: Design done , FPGA proven
WishBone Compliant: No
The SATA core implements the Command, Transport and Link Layers of
the SATA protocol and provides a Physical Layer Wrapper for the GTX
transceivers. The Physical Layer Wrapper also includes an Out of Band
Signaling (OOB) controller state machine which deals with initialization
and synchronization of the SATA link. It can interface with SATA 2
Winchester style Hard Disks as well as Flash-based Solid State Drives
The core provides a simple interface to issue READ/WRITE sector commands.
The DATA interface is 32-bit FIFO like.
A 150 MHz input reference clock is needed for the GTX transceivers.
The output data is delivered 4 bytes @ 75 MHz (user output clock).
A Xilinx base system with the SATA Core, a DDR interface and a Microblaze
C test application is also provided under "trunk/sata2_bus_v1_00_a"