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Source code

Details

Name: nysa_sata
Created: May 8, 2015
Updated: May 12, 2015
SVN Updated: May 11, 2015

Other project properties

Category: Communication controller
Language: Verilog
Development status: Beta
Additional info:
WishBone Compliant: No
License: Others

Description


Staus:


Simulations are working
Currently the stack is confusing to use, I'm working on this.
I do not intend to push developer versions of the code to opencores if you are interested in observing the developer cores I work primarily through github:
Nysa SATA Github
TODO: Modify Link layer so that it only instantiates one instance of a single scrambler, not two

Code Organization:


rtl/
sata_stack.v (Top File that applications interface with)
sata_defines.v (Set defines for the stack in here)
generic/ (small modules used throughout the design)/
blk_mem.v (wraps around an infered block memory generator) cross_clock_enable.v (simple module that allows users to send enables across a clock domain) debounce.v (debounce)
ppfifo.v (ping pong FIFO, similar to a ping pong buffer except the user doesn't need to track the addresses)

command/
sata_command_layer.v (Sata Command Layer)

transport/
sata_transport_layer.v (Sata Transport Layer)

link/
sata_link_layer.v (Sata Link Layer) sata_link_layer_read.v (Sata link layer read side) sata_link_layer_write.v (Sata link layer write side) scrambler.v (scrambles/descrambles primitives) crc.v (Cyclical Redundancy Check/ creator) cont_controller.v (controls the scrambling of primitives)

phy/
sata_phy_layer.v (Sata phy layer) oob_controller.v (out of band controller)

platform/
sata_platform.v (This is a template file you can use to interface with the gigabit transceivers)

To Use:
Currently the stack is complicated to use: The simulations show how it is intended to be used. I am working on both a wishbone and non-wishbone controller to simplify the process.

Soapbox:
Although I believe this code should be distributed for free and people should redistribute their software I leave the ethics up to the user and have licensed most of the code as MIT but I did use some GPL cores and if the user desires to use this in their closed source project be warned about the GPL'ed modules in this stack.