Go Back

Source code

Details

Name: virtex7_pcie_dma
Created: Dec 18, 2014
Updated: Apr 30, 2015
SVN Updated: Apr 30, 2015

Other project properties

Category: Communication controller
Language: VHDL
Development status: Beta
Additional info: FPGA proven , Specification done
WishBone Compliant: No
License: LGPL

Block Diagram

dma_core_structure

Description

The PCIe Engine is designed by Nikhef - Amsterdam, The Netherlands - for the ATLAS / FELIX project. Its main purpose is to provide a simple Direct Memory Access (DMA) interface to the Xilinx Virtex-7 PCIe Gen3 hard block. The Engine is specifically designed for the 256 bit wide AXI4-Stream interface of the Xilinx Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe) .

DMA read and write

The main purpose of the PCIe Engine is therefore to provide an interface to standard FIFOs. This is the done by the block in the diagram above. The read/write FIFOs have the same width as the Xilinx AXI4-Stream interface (256 bits) and run at 250 MHz. The application side of the FPGA design can simply read or write the FIFOs. The PCIe Engine will handle the transfer to Host PC memory, according to the addresses specified in the .

DMA control

Another functionality of the Engine is thus to manage a set of DMA descriptors. Descriptors consist of an address, a read/write flag, the transfer size (number of 32 bit words) and an enable line. Descriptors are handled by the block. These descriptors are mapped as normal PCIe memory or IO registers. Besides the descriptors and the enable line (one per descriptor), a status register for every descriptor is provided in the register map.

Generic regiser map

Besides DMA specific functions, the DMA control block can also handle generic and registers for user application.

Interrupt handler

The Engine is provided with a generic MSI-X compatible interrupt controller.

Implementation info

For synthesis and implementation of the cores, it is recommend to use Xilinx Vivado 2014.2. Other IP cores (FIFO, clock wizard and PCIe) are provided in the Xilinx .xci format, as well as the constraints file (.xdc) is in the Vivado 2014.2 Format. The Engine is also known to work well with Vivado 2014.4, constraints will be updated.

For portability reasons, no Xilinx project files will be supplied with the Engine. Instead, a bundle of has been supplied to create a project and import all necessary files, as well as to do the synthesis and implementation. These scripts are be described in details in the /documentation/pci_dma_core.pdf distributed with the Engine.

Feedback


>> Give comments and feedback using the official core thread on the OpenCores forum:
forum_thread