Created: Aug 6, 2010
Updated: Aug 7, 2010
SVN Updated: Aug 24, 2010
Other project properties
Development status: Beta
Additional info: Design done , FPGA proven , Specification done
WishBone Compliant: Yes
This core is part of the
, the most advanced open source SoC for interactive multimedia applications.
- Minimal 10/100 Ethernet MAC.
- Only full duplex support for now.
- DMA support (Wishbone master)
- Packets are streamed to and from system memory to minimize costly on-chip storage.
- Directly connects to standard MII PHYs.
- Bit-banged MDIO
- Core documentation
- CSR bus specifications