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Source code

Details

Name: manchesteruart
Created: Aug 10, 2014
Updated: Nov 12, 2014
SVN Updated: Nov 12, 2014

Other project properties

Category: Communication controller
Language: VHDL
Development status: Alpha
Additional info:
WishBone Compliant: No
License: LGPL

Description

This is a Manchester encoded UART that enables runing small periferals with parasitic power derived from the TXD line, and allowing large clock differences typical of RC oscillators.

ManchesterUart

What it is:
The Manchester UART replaces a standard UART. Instead of the NRZ coding of byte, it uses a Manchester protocol and encodes a 16 bit data word. The Manchester protocol transitions in the middle of the bit time. A rising transition is considered a one, and a falling transition is considered a zero. In order to get the correct edge in the middle of the bit time, there may be or may not be a transition at the beginning or end of a bit time. The Manchester UART is high when idle. The word is encoded similarly to a normal UART, with a start bit, 16 data bits (LSB first), and a stop bit. Start and stop bits are encoded as ones.
What it is not:
The Manchester UART is not a Manchester encoder/decoder. Manchester encoder/decoders have continuous transitions and require higher layers of protocol to construct frames and syncs.
Why you might use it:
The Manchester UART is most useful for communicating with devices that use the same lines for communication and power. Such a system is often referred to as parasitic power. Because the Manchester encoding has a maximum low pulse width of 1 bit time, as opposed to 9 bit times for a standard UART, you can use less capacitance to maintain the power during the lows of the communication stream. Another advantage is that the timing for the Manchester UART resyncs on every bit, whereas a standard UART syncs on the first edge of the start bit, and has to maintain the timing from that first edge to the sample of the stop bit, some 9.5 bit times later. This means the Manchester UART is much more tolerant of clock drifts, and can tolerate RC oscillators. The test bench actually simulates the clock differences between the transmitter and receiver, and can tolerate over plus or minus 18% clock rate differences.