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Source code


Name: madi_receiver
Created: Feb 14, 2009
Updated: May 5, 2015
SVN Updated: May 2, 2010

Other project properties

Category: Communication controller
Language: VHDL
Development status: Stable
Additional info: Design done , FPGA proven
WishBone Compliant: No
License: LGPL


This is a receiver for a Multichannel Audio Digital Interface (MADI), also known as AES-10. This type of fibreoptical or electrical connection is used in professional audio where a greater number of digital audio channel has to be transported.
The link speed of MADI is 125Mbit/s, while the data transfer rate used is 100Mbit/s. The diffrence between the two is explained by the use of a link encoding scheme. The encoding scheme used is known as 4B5B, which turns a 4 bit nibble into a 5 bit symbol. The data is NRZI encoded for a nearly DC-free link.
Clocking of this design is synchonous, a 25MHz clock signal has to be provided in order to receive the datastream. For synchronisation, a unique 2-symbol bit pattern is used, that can never occur in the payload of the data. The extra bandwidth between the payload speed and the data speed is filled with this bit pattern: 11000 10001 or symbols "JK" in 4B5B.
All of this seems very similar to a 100Mbit Ethernet connection. Therefore, an Ethernet PHY is used to receive the MADI datastream. The PHY must be able to output codegroups instead of 4 bit nibbles. A good example is the Cirrus Logic CS8952-CQZ. At the first stages of the development of MADI, AMD's TAXIchip transmitters ans receivers were used to establish the link. Nowadays, TAXIchips are outdated and nearly impossible to get, let alone use it in production. Cypress supposedly has some transceivers which also support the TAXIchip protocol.
The MADI protocol supports 56 or 64 channels of 48/44.1/32KHz digital audio, or half the number in double the sample clock. To achive an even higher sample rate, two or more channels can be combined for consecutive samples.
The design uses a wordclock output for MADI, and wordclock and bitclock input for ADAT. Thus, the design needs an external PLL block, which has a 48kHz input and is multiplied by 256 to get a bitclock. Take a look at the Cirrus Logic CS2100 for example. A PLL of such must be supplied externally in order for the design to work. If you try the make a clock multiplier in software, the ADAT signal would have too much jitter. The internal PLL in the Cyclone is not designed to use a 48kHz signal for an input (frequency is too low).
This design is now FPGA proven as I have developed a prototype board for this purpose. Interfacing to an RME HDSPe MADI soundcard, this prototype board accepts 8 ADAT inputs and turns them into a MADI signal, and converts a MADI steam into 8 ADAT outputs.


Photobucket This is the prototype board

Photobucket A closeup, always great to manually solder those QFP's

Photobucket The board in action on the logictap


- Slim design
- interface to readily available 100Mbit LAN PHY
- 25MHz clock input required
- Outputs appoximate wordclock
- Interfaces to 8x ADAT optical
- Supports frames of 20,4 us as well as 10,2 us
- Maximum of 64 digital audio channels
- Adapts to speed changes


- VHDL design done
- preliminary testbench created. This does not create a valid MADI signal, because the frame length is not according to specification. For now it will do the job.
- FPGA proven
- Minor adjustments may be neccesary