Go Back

Source code

Details

Name: jtag_master
Created: May 26, 2010
Updated: Jun 8, 2010
SVN Updated: Feb 6, 2011

Other project properties

Category: Communication controller
Language: VHDL
Development status: Alpha
Additional info:
WishBone Compliant: No
License: LGPL

Description

This is a JTAG Master written in VHDL. It's simulated and tested with XC9500 and the jtag slave from opencores ( http://opencores.org/project,jtag)