Created: Jan 20, 2009
Updated: Mar 17, 2011
SVN Updated: Mar 10, 2009
Other project properties
Development status: Beta
Additional info: Design done
WishBone Compliant: No
I2S to Parallel Interface
This module provides a bridge between an I2S serial device (audio ADC, S/PDIF Decoded data) and a parallel device (microcontroller, IP block).
It's coded as a generic VHDL entity, so developer can choose the proper signal width (8/16/24 bit)
-I2S Bit Clock
-I2S LR Clock (Left/Right channel indication)
-DATA_L / DATA_R parallel outputs
-STROBE and STROBE_LR output ready signals.
As soon as data is read from the serial I2S line, it's written on the proper parallel output and a rising edge of the STROBE signal indicates that new data is ready.
STROBE_LR signal tells if the strobe signal was relative to the left or right channel.
Parallel data (DATA_L / DATA_R) remain valid for the whole cycle (until next data is processed)
- Supports arbitrary data width (through the generic width parameter)
- 2009/01/20 : Uploaded Rev 1.0 and Testbench