Created: Jul 6, 2011
Updated: Nov 28, 2011
SVN Updated: Jul 7, 2011
Other project properties
Development status: Beta
WishBone Compliant: No
This is a quick module I hacked together to connect two I2C buses to work around a hardware bug on a board.
It mostly works, and I'm posting it in case others find it useful. I wouldn't use it in a production system as it stands.
It is written in SystemVerilog, so you'll need to change some "logic" declarations to "reg" if your compiler can't handle SystemVerilog. There are probably some other SystemVerilog features used, also.
I suggest toggling the reset signal between I2C transfers, if possible.