Created: Oct 29, 2008
Updated: Jun 10, 2012
SVN Updated: Jun 5, 2012
Other project properties
Development status: Stable
Additional info: Design done , FPGA proven
WishBone Compliant: No
Since lots of people ask me questions about my core, i want to clarify some things:
1) the master works, the slave is not entirely thought-through, i used it in simulation only.
2) i'm adding a diagram, that explains how to control the core.
3) adding a file name i2c_master_v01.vhd, that containes the master only.
4) since i have some time now, i will try to work on the slave.
The file name is V02 because V01 contained only an unwilling to work master.
it will not be posted here.
*supports burst writes and reads
*fully controlled by interface
for now i build a different interface for each use of the core.
in he future i plan to build a generic controller, that will act as a bridge from the PCI PLB to I2c.