Go Back

Source code

Details

Name: i2c_master_slave_core
Created: May 22, 2008
Updated: Dec 20, 2009
SVN Updated: Mar 10, 2009

Other project properties

Category: Communication controller
Language: Verilog
Development status: Stable
Additional info: FPGA proven
WishBone Compliant: Yes
License:

Description

Description of project..
This design is Wishbone compatible I2C core. This core can work as I2C master as well as slave.
VMM Test-bench is also available.

Features

Both Master and slave operation
Both Interrupt and non interrupt data-transfers
Start/Stop/Repeated Start generation
Fully supports arbitration process
Software programmable acknowledge bit
Software programmable time out feature
programmable address register
Programmable SCL frequency
Soft reset of I2C Master/Salve
Programmable maximum SCL low period
synthesis core

Status

Design: Done
VMM based verification Environment Creation: Done